| 摘要 |
There is provided a voltage comparator circuit with even lower power consumption. It comprises an FET Q 1, to the gate of which a signal input terminal IN 1 is connected, an FET Q 2, to the gate of which a signal input terminal IN 2 is connected, a bistable circuit, an AND circuit G, and an FET Q 11 . A pulse signal phi, which becomes a strobe signal for the comparison, is supplied to the bistable circuit, and when the pulse signal phi is at a low level, the logic values of output terminals OUT 1 and OUT 2 go to a high level, and the output of the AND circuit G becomes high, turning the FET Q 11 on. When the pulse signal phi changes to a high level from a low level, input voltages are compared, one of the output terminals OUT 1 or OUT 2 changes to a low level, corresponding to the value relationship between the drain currents of the FETs Q 1 and Q 2 , and the output of the AND circuit G goes to a low level, turning the FET Q 11 off. The power consumption is reduced because the source currents of the FETs Q 1 and Q 2 flow only during a short period of time when the operation of comparison is being performed.
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