| 摘要 |
An improved architecture for switches and a method for transmitting data with the switching are disclosed. An increased amount of memory is utilized, operating at speeds lower than are required by Input Queued switches, and a simple scheduling algorithm. The architecture divides the input ports into groups, where each input port group has an associated set of memory elements. Incoming packets are routed to the appropriate element in the set of memory elements. The number of groups and the number of ports that are included in each group can be varied, allowing the architecture to be modified based on the system architecture, the semiconductor technology, and other design considerations.
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