| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the cell area of a nonvolatile memory composed of single-layer polysilicon gates and, in addition, to enable the device to operate with ultra-low power consumption. <P>SOLUTION: The writing in the nonvolatile memory is performed by injecting hot electrons generated by an interband tunnel phenomenon into a floating gate 6 by impressing a reverse bias voltage, such as -5 V etc., upon a junction constituted of a p-type impurity region 8 provided on the substrate surface of an n-type well 4 in the lower portion of the end of the floating gate 6 through a gate oxide film 5 and the n-type well 4. Since the writing time can be designed to about 10 μs and the leak current of the junction at writing time can be designed to about 100 nA, the energy required for writing is reduced to 5 pJ. Therefore, the writing energy to the nonvolatile memory can be reduced to ≤1/100 of the writing energy to the conventional stacked gate type memory cell using channel hot electron injection. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
