| 摘要 |
PURPOSE:To extract a clock rising in the timing in the middle of a period when an RZ data input signal is at a high level by providing a duty adjustment means of a voltage controlled oscillator to the phase locked loop circuit. CONSTITUTION:An output of a buffer 4 inserted in a feedback loop is integrated by a filter 6 via a buffer 5 and an integration voltage adjusts the duty ratio of the output of the buffer 4. When the duty ratio of the output of the buffer 4 is controlled to be a prescribed value larger than the duty ratio of the RZ data input signal, an output voltage when an edge of an extracted clock is resident in the middle of a high level period of the RZ data input signal is constant and the clock rising in the timing in the middle of a period when the RZ data input signal is at a high level is extracted regardless of the duty ratio of the RZ data input signal. |
