| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce the rate at which a bus controller wastes power, while guaranteeing the responsiveness of the bus controller to access requests. <P>SOLUTION: The bus controller (7) has a detection circuit (23) for detecting access requests and a control circuit (32) for controlling bus access in response to the detection of an access request by the detection circuit. The bus controller renders the control circuit operable in synchronism with a clock signal in response to the detection of an access request by the detection circuit, and stops the operation of the control circuit synchronized with the clock signal, by ending bus access control that responds to the access request. In a form of autonomous control over the clock-synchronized operation of the control circuit, the bus controller renders the control circuit operable in synchronism with the clock signal by opening a transmission path of the clock signal to the control circuit, and stops the operation of the control circuit synchronized with the clock signal, by blocking the transmission path. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
