| 摘要 |
A PWM inverter in which a high surge voltage is prevented from being applied between the terminals of a switching element by preventing multiple phase simultaneous switching. A simultaneous switching preventing circuit (100), comprising a plurality of input means receiving a polyphase control signal from a PWM signal generating circuit as an input signal, a shielding pulse generating means generating a pulse for shielding the rising of input signals of other phases in respective specified periods depending on the rising of the input signal of each phase, a shielding signal forming means outputting a signal having a shielding period equal to the logical sum of a plurality of shielding pulses from the shielding pulse generating circuits of other phases, a signal shielding means receiving an input signal of one phase and outputting a signal having a rising delayed up to the end of the shielding period of an output signal from the shielding signal forming means, and a plurality of output means for delivering the output signal from the signal shielding means to the outside, is inserted between a gate drive circuit (3) and a three-phase PWM signal generating circuit (1). |
