| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To accelerate data transfer through a memory without increasing hardware. <P>SOLUTION: The integrated circuit device 10 comprises a memory controller 30, an input control circuit 20, a data transfer control circuit 40, and an output control circuit 50. The input control circuit 20 generates a write enable signal 22 and transmits the signal 22 to the data transfer control circuit 40 during a write enable period in which input data 12 is validly written through the memory controller 30 and the data transfer control circuit 40 is constituted so as to receive the write enable signal 22, generate an output request signal 42 of a cycle corresponding to the write enable signal 22 and transmit the output request signal 42 to the output control circuit 50 in parallel with the reception of the write enable signal 22. The output control circuit 50 recognizes the number of data to be read out from a memory 70 and transferred on the basis of the output request signal 42 and reads out and outputs the data through the memory controller 30. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
