Memory module e.g. single in-line memory module, has selection circuit which outputs non-periodic clock signal to memory and register, and register which controls address data of memory in synchronization with received signal

摘要

A clock selection circuit receives non-periodic clock signal (ELCK2) from external memories (M1-Mn), and internal periodic clock (ELCK1) from phased locked loop (PLC), and mode select signal (MSS). The clock selection circuit outputs non-periodic clock signal to memory and register based on mode select signal. The register controls the address information of memory in synchronization with received signal. Independent claims are also included for the following: (1) hub on memory module; (2) memory unit; (3) method of supplying clock to memory module; and (4) generation method of internal clock in memory module memory system.