发明名称 |
DESIGN RULE CHECKING SYSTEM |
摘要 |
<p>In a design rule checking system (10) for checking whether or not an integrated circuit design complies with design rules specifying limit values for respective geometric parameters, non-binary functions are used to model the way in which systematic yield loss varies with the value of the geometric parameters. This enables a value to be assigned to systematic yield loss in cases where the geometric parameter is compliant with the design rule but takes a value close to the design rule limit.</p> |
申请公布号 |
WO2006024324(A1) |
申请公布日期 |
2006.03.09 |
申请号 |
WO2004EP11076 |
申请日期 |
2004.08.31 |
申请人 |
FREESCALE SEMICONDUCTOR, INC.;RIVIERE, CAZEAUX, LIONEL |
发明人 |
RIVIERE, CAZEAUX, LIONEL |
分类号 |
(IPC1-7):G06F17/50 |
主分类号 |
(IPC1-7):G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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