| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a data write-in circuit of a semiconductor memory apparatus in which a multi-bit write-in system can be adopted even if a long time is required for data input. <P>SOLUTION: This apparatus is provided with a multi-bit decoder and data latch circuit 4 which latches successively data DQ being a plurality of data written respectively in a plurality of memory cells of the multi-bit and is inputted successively according to change of an input multi-bit address MBA, a column decoder 5 applying the latched plurality of data respectively to sources of the plurality of memory cells according to a column address in an input address ADD, and a cell drain voltage generator 7A in which when the all plurality of data are latched and applied to the sources of the plurality of memory cells, high cell drain voltage CDV (approximately 5.0V) for data write-in is applied simultaneously to drains of the plurality of memory cells, and the plurality of data are written respectively in the plurality of memory cells. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
