| 摘要 |
<p>PURPOSE:To provide a DSP device capable of substantially shortening computation time. CONSTITUTION:Since two data transfer processings are executed in one machine cycle, the number of the machine cycles required for completing data required for a processing such as an addition processing or the like for instance is reduced and thus, an operation speed is accelerated. Also, since a second RAM 14 for preserving the data for specifying the address of a first RAM 21 storing processing data is provided and a parameter for specifying two addresses of the second RAM 14 is defined in an instruction word, two data transfer processings are executed in one machine cycle, the number of the machine cycles required for completing the data required for the processing such as the addition processing or the like for instance is reduced and thus, the operation speed is accelerated.</p> |
