发明名称 |
Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance |
摘要 |
In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.
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申请公布号 |
US7008835(B2) |
申请公布日期 |
2006.03.07 |
申请号 |
US20040985246 |
申请日期 |
2004.11.10 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JIN YOU-SEUNG;AHN JONG-HYON;RYU HYUK-JU |
分类号 |
H01L21/336;H01L21/00;H01L21/28;H01L21/8234;H01L29/423;H01L29/49;H01L29/78 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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