发明名称 |
Data transmission/reception system |
摘要 |
In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system ( 12 ), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system ( 13 ), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system ( 10 ), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system ( 11 ) is realized.
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申请公布号 |
US7009426(B2) |
申请公布日期 |
2006.03.07 |
申请号 |
US20040513965 |
申请日期 |
2004.11.10 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
DOSHO SHIRO;TOKUNAGA YUSUKE;DOI YASUYUKI;NAKAGAWA HIROFUMI;DATE YOSHITO;OHMORI TETSURO;NISHIKAWA KAORI |
分类号 |
H03K19/00;G09G3/36;H04L25/02;H04L25/49 |
主分类号 |
H03K19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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