发明名称 TESTER ARCHITECTURE FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUITS
摘要 A modular tester architecture (100) allows end-users to mix-and-match scan chain modules and clock driver modules. Modules are interconnected via a synchronization bus (118) allowing the test modules to synchronize with each other so that each can perform its portion of the overall test at the proper time in relation to the testing performed by other modules. The modules can include a BIST driver module, a data acquisition module (208), networking interface modules (202), a controller module (204), a current measurement module (210), and a DC parametrics module.
申请公布号 KR20060019552(A) 申请公布日期 2006.03.03
申请号 KR20057022359 申请日期 2005.11.22
申请人 TESEDA CORPORATION 发明人 LIMAYE AJIT M.;DECHER PETER H.;NIEHAUS HORST ROLAND
分类号 G01R31/28;G01R31/3185 主分类号 G01R31/28
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