| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a signal processor capable of reducing the using number of PLL circuits. <P>SOLUTION: The signal processor has a reference clock generation circuit 8 which generates a reference clock CLK1 used as synchronous reference of signal processing, a counter 6 which counts the reference clock CLK1, and a frequency control circuit 5a which samples the count value of the counter 6 using an input clock from the outside, compares an incremental value IV from the previous sample value with an expected value, and controls frequency of the reference clock CLK1 according to a comparison result. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
