| 摘要 |
PROBLEM TO BE SOLVED: To shorten a test time by reducing the number of S-FF of a signal scan pass by half. SOLUTION: A semiconductor integrated circuit connects an input and output terminal 1A to the scan passes 3<SB>1</SB>-3<SB>m</SB>and a combination circuit 2 via a selector 5A, and connects an output side of the scan passes 3<SB>1</SB>-3<SB>m</SB>to an input and output terminal 1B via a selector 6A and a tristate buffer 7A. The semiconductor integrated circuit connects the input and output terminal 1B to scan passes 3<SB>m+1</SB>-3<SB>n</SB>and the combination circuit 2 via a selector 5B, and connects the output side of the scan passes 3<SB>m+1</SB>-3<SB>n</SB>to the input and output terminal 1A via a selector 6B and a tristate buffer 7B. At testing, the tristate buffers 7A and 7B are in an off-state, the input and output terminals 1A and 1B are connected to the scan passes 3<SB>1</SB>-3<SB>m</SB>and 3<SB>m+1</SB>-3<SB>n</SB>respectively to input test data. Thereafter, the signals of the combination circuit 2 are fetched in each S-FF3, the tristate buffers 7A and 7B are in an on-state, to be read from the input and output terminals 1B and 1A. COPYRIGHT: (C)2006,JPO&NCIPI
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