| 摘要 |
During an erasing sequence, after a preprogram operation (S 1 ), an erasing operation (S 3 ), and an APDE operation (S 5 ) are executed and confirmation by an APDE verify operation (S 6 : P) and confirmation by an erase-verify operation (S 7 : P) are completed, step A is executed prior to a soft-program operation (S 10 ) of a plurality of memory cells. A dummy memory cell program operation (S 8 ) is continuously executed until a completion of a program operation is confirmed by a dummy memory cell program verify operation (S 9 ). By execution of the program operation on the dummy memory cells, a voltage stress similar to that of a program operation is applied to memory cells in an over-erased state via bit lines. Thereby, the over-erased state is reduced thereby lowering a column leak current. Erroneous recognition during a soft-program verify operation (S 11 ) can be prevented, and excessive soft-programming can be avoided.
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