发明名称 |
Vertical transistor structures having vertical-surrounding-gates with self-aligned features |
摘要 |
The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.
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申请公布号 |
US2006043471(A1) |
申请公布日期 |
2006.03.02 |
申请号 |
US20040928522 |
申请日期 |
2004.08.26 |
申请人 |
TANG SANH D;HUGLIN GRANT S |
发明人 |
TANG SANH D.;HUGLIN GRANT S. |
分类号 |
H01L29/76 |
主分类号 |
H01L29/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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