| 摘要 |
A field programmable gate array (FPGA) for multiplexing data and enable signals input from a plurality of input ports and outputting the multiplexed signal to one output port is disclosed. The FPGA includes a plurality of memories, which are connected to the input ports, for storing the input data and enable signals, respectively, and outputting one-shot signals at trailing edges of the enable signals; and a finite state machine (FSM) for sequentially reading the data signals stored in the memories in an order of the one-shot signals input from the memories.
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