发明名称 HIGH VOLTAGE TOLERANCE OUTPUT STAGE
摘要 An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.
申请公布号 US2006044015(A1) 申请公布日期 2006.03.02
申请号 US20050162001 申请日期 2005.08.25
申请人 LEE CHAO-CHENG;LIN YUNG-HAO;WANG WEN-CHI;TSAI JUI-YUAN 发明人 LEE CHAO-CHENG;LIN YUNG-HAO;WANG WEN-CHI;TSAI JUI-YUAN
分类号 H03K19/0175 主分类号 H03K19/0175
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