Semiconductor memory with select line clamping circuit for preventing malfunction

摘要

In a DRAM, an N-channel MOS transistor (9) is connected between a forward end portion of each column selection line (CSL) and a signal transmission line (7) for transmitting a sense amplifier driving signal (/SE). The N-channel MOS transistor (9) is brought into a conducting state in a period when the signal (/SE) goes low for activation and a column decoder (3) is inactivated. Thus, a disconnected defective column selection line (CSL) can be prevented from being charged at a high level and causing a malfunction of the DRAM. Further, no specific line (58) of a ground potential GND may be provided for the N-channel MOS transistor (9) dissimilarly to the prior art, whereby the layout area can be reduced.