发明名称 Pipelined A/D converter and method for correcting error in output of the same
摘要 <p>Two capacitors in a variable stage are controlled from outside to function as a feedback capacitor and a sampling capacitor, respectively. With a test signal being supplied to the variable stage from an input selecting section, a stage evaluation section estimates an error in the output of the variable stage based on a difference between the digital outputs of an output correction section produced in two situations in which the functions of the two capacitors in the variable stage are switched. A correction value calculation section calculates a digital correction value for each variable stage based on the estimated error and an intermediate output of a digital calculation section. The output correction section corrects the digital output of the digital calculation section based on these digital correction values.</p>
申请公布号 EP1630964(A2) 申请公布日期 2006.03.01
申请号 EP20050018301 申请日期 2005.08.23
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 DOSHO, SHIRO;MORIE, TAKASHI;OGITA, SHINICHI;OHTANI, MITSUHIKO
分类号 H03M1/10 主分类号 H03M1/10
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