发明名称 |
Timing circuit with dual phase locked loops |
摘要 |
A timing circuit for generating clock signals, includes an acquisition digital phase locked loop with a wide capture range for closely following an input signal with its associated disturbances. An output digital phase locked loop having a slow response relative to the acquisition phase locked loop tracks an output of the acquisition phase locked loop to generate an output signal for the timing circuit.
|
申请公布号 |
US7006590(B2) |
申请公布日期 |
2006.02.28 |
申请号 |
US20010865504 |
申请日期 |
2001.05.29 |
申请人 |
ZARLINK SEMICONDUCTOR INC. |
发明人 |
SKIERSZKAN SIMON;VAN DER VALK ROBERT |
分类号 |
H03D3/24;H03L7/07;H03L7/23;H04B1/38;H04L7/00;H04L7/033;H04L25/00 |
主分类号 |
H03D3/24 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|