发明名称 |
LOOP DRIVER FOR POTS, XDSL, OR INTEGRATED POTS/XDSL INTERFACE |
摘要 |
A driver circuit comprising a transformer having a primary winding for coupling to a subscriber loop and a secondary winding for coupling to an interface circuit, a feedback circuit for coupling said primary winding to said secondary winding to provide a predetermined impedance match between said interface circuit and said loop over a predetermined frequency band of said circuit. In a preferred embodiment, the interface circuit is an integrated line card for supporting both POTS and ADSL.
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申请公布号 |
CA2274171(A1) |
申请公布日期 |
2000.12.10 |
申请号 |
CA19992274171 |
申请日期 |
1999.06.10 |
申请人 |
CATENA TECHNOLOGIES |
发明人 |
FEELEY, MARK |
分类号 |
H04Q3/42;H03F1/56;H04L27/00;H04L27/26;H04M11/00;H04M11/06;(IPC1-7):H04M7/04 |
主分类号 |
H04Q3/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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