发明名称 Wiring structure to minimize stress induced void formation
摘要 A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of "n" overlapping segments and at least one bending portion. The other end of the protrusion is connected to the bottom of a via which has an overlying second conducting layer. A bend is formed by overlapping the ends of two adjacent segments at an angle between 45° and 135°. The protrusion may also include at least one extension at a segment end beyond a bend. A bending portion and extension are used as bottlenecks to delay the diffusion of a vacancy from the large area portion to the vicinity of the via and is especially effective for copper interconnects or in a via test structure.
申请公布号 SG119259(A1) 申请公布日期 2006.02.28
申请号 SG20040007740 申请日期 2004.12.27
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 CHIEN-JUNG WANG;SU-CHEN FAN;DING-DAR HU;HSUEH-CHUNG CHEN
分类号 H01L23/52;H01L27/148 主分类号 H01L23/52
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