发明名称 |
Computer power optimization by speculative calling-up and clearing of data in a computer processor cache memory bank, in which orders can be carried out in an un-ordered fashion so reducing cache coherence latency |
摘要 |
Device comprises a cache coherence test device assigned to the first of a number of processors, which is configured to generate a presence signal, a pre-clearing slot for use with the cache memory of the multiple processors and software for controlling the pre-clearance slot and the cache memory. An Independent claim is made for a method for minimizing cache coherence latency in a multi-processor system.
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申请公布号 |
DE10113191(A1) |
申请公布日期 |
2001.11.08 |
申请号 |
DE20011013191 |
申请日期 |
2001.03.19 |
申请人 |
HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE), PALO ALTO |
发明人 |
LESARTRE, GREGG B.;JOHNSON, DAVID JEROME |
分类号 |
G06F9/38;G06F12/08;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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