发明名称 RECEIVER AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To surely execute processing according to a received reply signal. <P>SOLUTION: Received signals S20 and S50 based on the reply signal are passed through high-pass filters 4 and 57 to generate high-band signals S22 and S52, and offset comparators 40 and 61 generate demodulation signals S27 and S55 using timing in which potential difference after detection of signal intersections SCP2 and SCP5 between the high-band signals S22 and S52 and reference signals S25 and S53 coincides with offset potential difference as change timing of logical levels. Thus, even if the high-band signal S22 and S52 in which signal intersections SCP3 and SCP5 which do not originally exist arise are generated by the high-pass filters 4 and 57, the demodulation signals S27 and S55 having change points of the logical levels according only to original signal intersections SCP2 and SCP4 are generated to execute the processing according to contents of the reply signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006054859(A) 申请公布日期 2006.02.23
申请号 JP20050196363 申请日期 2005.07.05
申请人 SONY CORP 发明人 ARISAWA SHIGERU;EZAKA SEIJI;KITA MASATAKA
分类号 H04B5/02;G06K19/07;H04B1/59 主分类号 H04B5/02
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