| 摘要 |
PURPOSE: A structure of an input circuit is provided to be capable of effectively optimizing the characteristics of an input by independently controlling the characteristics of the input circuit. CONSTITUTION: A buffer(51) consists of hysteresis type MOS transistors determining the logic of input signals in accordance with a logic reference voltage. A first fuse(52) controls the characteristics of the buffer(51) to regulate the logic reference voltage of the buffer. A first delay(53) delays the output signal of the buffer by first time. A second delay(54) delays the output signal of the buffer by second time longer than the first time. A second fuse(57) adjusts the durations of the first time and the second time. A MUX(55) selects the output signal of the first delay in accordance with an external clock signal and then selects the output signal of the second delay. A latch(56) latches the output signal of the MUX in accordance with the external clock signal.
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