Transferring information for data communicated between integrated circuits has receive circuit adapted to sample the data signal in response to rising and falling transitions of the data sampling signal

摘要

A variable delay circuit to generate a data sampling signal (DQ1-DQN) that is delayed relative to a reference clock signal according to a delay control signal; a control circuit coupled to receive the data sampling signal from the variable delay circuit and a timing reference signal from a data transmitting device, the control circuit including circuitry to determine a phase difference (55) between the data sampling signal and the timing reference signal has a number of rising transitions and falling transitions, and to generate the delay control signal according to the phase difference which is approximately ninety degrees. A receive circuit is adapted to sample the data signal in response to rising and falling transitions of the data sampling signal and coupled to receive the data sampling signal from the variable delay circuit and to a data signal from the data transmitting device, the receive circuit including circuitry to sample the data signal in response to a transition of the data sampling signal. An independent claim is also included for A system for transferring information.