发明名称 Latency-aware replacement system and method for cache memories
摘要 A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is likely to be evicted from the cache. Among a group of highest ranking cache lines in a cache set, the cache line chosen to be replaced is one that provides the lowest latency access to a requesting entity, such as a processor. The distance separating the requesting entity from the memory partition where the cache line is stored most affects access latency.
申请公布号 US2006041720(A1) 申请公布日期 2006.02.23
申请号 US20040920844 申请日期 2004.08.18
申请人 HU ZHIGANG;REOHR WILLIAM R 发明人 HU ZHIGANG;REOHR WILLIAM R.
分类号 G06F12/00 主分类号 G06F12/00
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