发明名称 |
Semiconductor memory device capable of high speed input/output of wide bandwidth data by improving usage efficiency of external data bus |
摘要 |
Serial write data of the burst length transmitted to a data bus are stored in parallel in latch circuits by a S/P data conversion circuit. In a memory cell array, one row of memory cells and four columns of memory cells are rendered active at the same time. Respective bit lines and latch circuits are connected by a sense amplifier I/O circuit. The write data of the burst length are written into the memory cell array at one time. The data of the bit length read out at one time from the memory cell array are converted into serial data by a P/S data conversion circuit to be transmitted to the data bus.
|
申请公布号 |
US6396747(B2) |
申请公布日期 |
2002.05.28 |
申请号 |
US19990461093 |
申请日期 |
1999.12.14 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
KUBO TAKASHI;IWAMOTO HISASHI |
分类号 |
G11C11/401;G11C7/00;G11C7/10;G11C11/407;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|