| 摘要 |
A DC symmetrical FET switch includes second and third switches connecting the well of the symmetrical FET switch to the drains and the source when the symmetrical FET switch is on. When the three FET's are on, the well, source and drain of the symmetric FET switch all exhibit the same input signal, wherein the drains and source to well capacitances are substantially prevented from draining off any of the input signal, thereby increasing the bandwidth and decreasing the insertion loss of the switch. The second and third switches are also FET switches. An enable signal is connected to the gates of all three FET's turning them on and off together. When the enable is false the FET switches are turned off and their wells are driven to a potential a proper potential. When the FET's are n-type the potential is low and when the FET's are p-types the potential is high. A resistor is provided in the gate drive of the first FET switch that further increases bandwidth and decreases insertion loss of the switch by moving the break frequency of the drain and source to gate capacitances.
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