| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an interleave timing generator less in power consumption. <P>SOLUTION: The timing generator comprises a set reset latch, a set section for supplying a set signal, and a reset section for supplying a reset signal. The set section comprises a first variable delay circuit for outputting a first set signal where a given reference clock is delayed; a second variable delay circuit for outputting a second set signal where the given reference clock is delayed, and the phase differs from that of the first set signal; an OR-circuit for calculating the OR between the first and the second set signals and generating the set signal; and a third variable delay circuit for delaying the set signal outputted by the OR-circuit, and for adjusting the skew between the set and the reset signals. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
