| 摘要 |
An integrated circuit has a memory block including a RAM macro, a first scan circuit and a second scan circuit having a plurality of SFFs, and a serial access memory BIST circuit. The first scan circuit has an input scan FF group capable of supplying data to the memory block and the second scan circuit has an output scan FF group capable of receiving data from the memory block. In a first test mode, a normal scan test is performed. In a second test mode, the serial access memory BIST circuit outputs a BIST signal serially, and a selector selects and supplies the BIST signal to the input scan FF group, thereby testing the memory block.
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