发明名称 |
Method and system for reducing pin count in an integrated circuit when interfacing to a memory |
摘要 |
The invention provides a system and method for reducing pin count in an integrated circuit (IC) when interfacing to a synchronous dynamic random access memory (SDRAM). The SDRAM has a plurality of address lines and a plurality of data lines. The method includes connecting together the plurality of data lines and the plurality of address lines. The IC interfaces to the SDRAM through the connected plurality of address lines and the plurality of data lines.
|
申请公布号 |
US2006041713(A1) |
申请公布日期 |
2006.02.23 |
申请号 |
US20040920975 |
申请日期 |
2004.08.18 |
申请人 |
CHARLES GORDON;WASHINGTON EMANUEL |
发明人 |
CHARLES GORDON;WASHINGTON EMANUEL |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|