| 摘要 |
PROBLEM TO BE SOLVED: To shorten a period of manufacture and reduce a cost by reducing the number of sheets of additional masks needed to subject a nonvolatile memory to a standard CMOS logic process. SOLUTION: In a split gate type memory cell utilizing a side wall structure with a silicided gate electrode, an isolated auxiliary pattern 22 is disposed adjacently to a selection gate electrode 12. Polysilicon of the side wall gate is filled in a gap between the selection gate electrode and the isolated auxiliary pattern, and a contact 21 is provided for a wiring part 23 formed in a self alignment manner. The contact 21 may be overlapped on the auxiliary pattern 22 and an element isolation region, whereby a design is optimized taking an occupation area into consideration. Assuming a distance between the contact and the selection gate electrode 12 to be x, a deposition thickness of an ONO film t, and a deposition thickness of the polysilicon film d, the auxiliary pattern 22 may be disposed while separating by the distance x satisfying a relation: x<2×(t+d). COPYRIGHT: (C)2006,JPO&NCIPI
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