Semiconductor memory circuit hard to cause soft error

摘要

A memory cell of SRAM includes: two N-channel MOS transistors connected in series between a first storage node and a line of a ground potential and two N-channel MOS transistors connected in series between a second storage node and a line of a ground potential. Since no storage data is inverted unless one alpha-particle passes through two N-channel MOS transistors, a soft error hard to occur.