High precision data and clock output circuit

摘要

An output circuit of the present invention includes a data output circuit and a clock output circuit. The output circuit includes a first D-type flip-flop and a selector for selectively outputting an output from the first D-type flip-flop or second data according to a selection signal. The clock output circuit includes a second D-type flip-flop, a third D-type flip-flop, and a dummy selector circuit. The dummy selector circuit is connected to the second and third D-type flip-flops and outputs a clock signal by using the same elements as those of the selector in order to realize the same delay time as that of the selector.