发明名称 Switched capacitor circuit capable of minimizing clock feedthrough effect and having low phase noise and method thereof
摘要 A switched capacitor circuit includes a capacitor; a switch element for selectively coupling a first node to a second node according to a control signal, wherein the first node is coupled to the capacitor; and a charge circuit coupled to the first node for coupling the first node to a third node and for controlling a first voltage difference across the first switch element in the off-state to be greater than a charge voltage. By ensuring the charge voltage is large enough to minimize a parasitic capacitance of the switch element, the clock feedthrough effect is eliminated, the locking period of the VCO is shortened, and the phase noise of the VCO is minimized.
申请公布号 US7002393(B2) 申请公布日期 2006.02.21
申请号 US20040708700 申请日期 2004.03.19
申请人 MEDIATEK INC. 发明人 YEH EN-HSIANG
分类号 G06G7/18;H03B5/04;H03L7/06;H03L7/099;H03L7/10;H03L7/16 主分类号 G06G7/18
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