发明名称 SIMULATION METHOD
摘要 PROBLEM TO BE SOLVED: To provide a simulation method capable of reducing the time to verify the logic operations of LSI by automatically creating a data input/output circuit between an untimed operation model and a mounted logic circuit. SOLUTION: The simulation method includes a step in which a mounting part creates data on the logic circuit mountable in a rewritable semiconductor device in order to execute the logic operations achieved by hardware; a step in which the mounting part creates data on the input/output circuit mountable in the semiconductor device in order to execute input/output operations included in the logic operations achieved by software; and a step in which a verifying part verifies the logic operations of a semiconductor integrated circuit using the logic circuit mounted in the semiconductor device according to the logic circuit data, the input/output circuit mounted in the semiconductor device according to the input/output circuit data, and the untimed operation model for executing the logic operations achieved by the software, the untimed operation model having no time setting description. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006048525(A) 申请公布日期 2006.02.16
申请号 JP20040231289 申请日期 2004.08.06
申请人 TOSHIBA CORP 发明人 TAKEI TSUTOMU
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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