| 摘要 |
PROBLEM TO BE SOLVED: To provide an algorithm pattern generator for a memory element test and enabling to optimize the constitution of a memory tester that includes address scrambling and data scrambling. SOLUTION: The generator comprises an instruction memory for storing a test program; a sequence control part which fetches the instruction of the test program from the memory one by one; an interface unit with an external device; PLL which forms and offers the clock signal of the same phase; a command generation part which forms a command required for the test to each clock cycle; an address generating part which forms the address required for the test by the address scrambling for each clock cycle and a data generation part which forms the data required for the test by the data scrambling; and a data comparison part for storing information with respect to defect memory, by comparing the data which is formed at the data generation part and the test data for each clock cycle. COPYRIGHT: (C)2006,JPO&NCIPI
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