发明名称 |
Error recovery in asynchronous combinational logic circuits |
摘要 |
A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.
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申请公布号 |
US2006033523(A1) |
申请公布日期 |
2006.02.16 |
申请号 |
US20040891654 |
申请日期 |
2004.07.15 |
申请人 |
HONEYWELL INTERNATIONAL INC. |
发明人 |
ERSTAD DAVID O.;CARLSON ROY M. |
分类号 |
H03K19/003 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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