发明名称 Method and apparatus for jitter analysis and program therefor
摘要 A method, an apparatus and a program for comprehensively analyzing the power supply noise and consequent jitter for external output signals of the LSI in real time. From LSI layout designing data 601, the resistance, capacitance and inductance of the power supply interconnection are extracted to formulate a power supply LRC model 606. An analysis model formulating unit 812 connects a transistor model 610, a noise source model 607, a silicon substrate model 608 and a package/board (printed circuit board) model 611 to formulate a model for analysis of the power supply noise 813 and a model for jitter analysis 817. An analysis unit 814 acquires power supply noise waveform data 816 by first simulation and also acquires jitter analysis data 815 using power supply noise waveform data 816 by second simulation.
申请公布号 US2006036980(A1) 申请公布日期 2006.02.16
申请号 US20050183070 申请日期 2005.07.18
申请人 NEC ELECTRONICS CORPORATION 发明人 KOBAYASHI SUSUMU
分类号 G06F17/50 主分类号 G06F17/50
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