发明名称 |
DIGITAL FREQUENCY LOCKED DELAY LINE |
摘要 |
<p>A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.</p> |
申请公布号 |
WO2006017723(A1) |
申请公布日期 |
2006.02.16 |
申请号 |
WO2005US27863 |
申请日期 |
2005.08.05 |
申请人 |
MICRON TECHNOLOGY, INC.;SCHNARR, CURT |
发明人 |
SCHNARR, CURT |
分类号 |
(IPC1-7):H03L7/081 |
主分类号 |
(IPC1-7):H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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