| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device and to improve a manufacturing yield. <P>SOLUTION: Memory cells 30 are arranged in the shape of plural arrays, and selector gate electrodes 8 of the memory cells 30 which are lined up in the X direction are connected by selector gate lines 9. Memory gate electrodes 13 are connected by memory gate lines 14. Memory gate lines 14 connected to the memory gate electrodes 13 of the adjacent memory cells 30 through source regions 20 are not electrically connected, respectively. The selector gate line 9 has a first part 9a extending in the X direction, and a second part 9b extending in the Y direction whose one end is connected with the first part 9a. The memory gate line 14 is formed on a side wall of the selector gate line 9 through an insulating film, is provided with a contact 14a extending in the X direction from the second part 9b of the selector gate line 9 to an element isolation region, and is connected to a wiring through a plug burying a contact hole 23d formed on the contact part 14a. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
