SEMICONDUCTOR STORAGE DEVICE

摘要

The present invention relates to semiconductor storage devices such as memory cells and latches, and its purpose is to provide memory cells or the like that have a high immunity against soft errors. P-type and N-type transistors constituting inverters are paired, and the paired P-type and N-type transistors are disposed on each of separate wafers. The invention comprises four pairs of P-type and N-type transistors coupled to each other; and gate-to-node connection wires that connect nodes, each of which couples the P-type and N-type transistors of a respective pair, with the gates of P-type and N-type transistors in such a direction that prevents a potential inversion, which would occur at a node due to a soft error, from propagating to another node.