SUB-RANGING PIPELINED CHARGE-DOMAIN ANALOG-TO-DIGITAL CONVERTER WITH IMPROVED RESOLUTION AND REDUCED POWER CONSUMPTION

摘要

A pipelined analog-to-digital converter in which signal value samples are represented differentially by pairs of charges and which uses charge-coupled-devices (CCDs) for delay and arithmetic operations on the charges is presented. In the pipeline, each successive stage resolves an equal or smaller charge difference. After a certain number of pipeline stages, the common-mode component of the signal-charge pair is reduced. The pipeline stages following this common-mode-charge reduction stage have a reduced charge capacity and size, allowing more sensitive charge comparison. The result is improved A/D converter resolution and reduced power consumption.