Simplification of the reset function of a multi processor computer system using data loaded into Cache memory

摘要

The computer system [10] has multiple CPU units [12] that each have a Cache memory [14] that can be of the SRAM or DRAM type. The Cache stores address and status data when a reset condition occurs. An interface [16] handles part of the reset sequence to obtain instructions from a memory [22] to facilitate the reset process.