| 摘要 |
A digital high frequency power detection circuit includes a peak detecting circuit and a peak computing circuit. The peak detecting circuit is operably coupled to detect a peak value of a high frequency signal and includes an amplifier, transistor, and capacitor. The amplifier has a 1s<SUP>t </SUP>input, 2<SUP>nd </SUP>input and an output, where the 1<SUP>st </SUP>input is operably coupled to receive the high frequency signal. The transistor has a gate, a drain, and a source, where the gate is coupled to the output of the amplifier, the source is coupled to a supply voltage, and the drain is coupled to the 2<SUP>nd </SUP>input of the amplifier. The capacitor is operably coupled to the drain of the transistor and to a reference potential. The voltage imposed across the capacitor represents the peak value of the high frequency signal. The peak computing circuit is operably coupled to generate a digital peak value from the peak value.
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