发明名称 |
Redundancy register architecture for soft-error tolerance and methods of making the same |
摘要 |
A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a "don't care" state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.
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申请公布号 |
US7000155(B2) |
申请公布日期 |
2006.02.14 |
申请号 |
US20030249574 |
申请日期 |
2003.04.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
OPPOLD JEFFERY H.;OUELLETTE MICHAEL R.;WISSEL LARRY |
分类号 |
G11C29/00;G11C5/00;G11C11/412 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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